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Semiconductor MSM6242B
Semiconductor DESCRIPTION
The MSM6242B is a silicon gate CMOS Real Time Clock/Calendar for use in direct busconnection Microprocessor/Microcomputer applications. An on-chip 32.768 KHz crystal oscillator time base is divided to provide addressable 4-bit I/O data for SECONDS, MINUTES, HOURS, DAY OF WEEK, DATE, MONTH and YEAR. Data access is controlled by 4-bit address, chip selects (CSO, CS1), WRITE, READ, and ALE. Control Registers D, E and F provide for 30 SECOND error adjustment, INTERRUPT REQUEST (IRQ FLAG) and BUSY status bits, clock STOP, HOLD, and RESET FLAG bits, 4 selectable INTERRUPTS rates are available at the STD.P
MSM6242B
DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR
(STANDARD PULSE) output utilizing Control Register inputs T0, T1 and the ITRPT/ STND (INTERRUPT/STANDARD). Masking of the interrupt output (STD.P) can be accomplished via the MASK bit. The MSM6242B can operate in a 12/24 hour format and Leap Year timing is automatic. The MSM6242B normally operates from a 5V 10% supply at -40 to 85C. Battery backup operation down to 2.0V allows continuation of time keeping when main power is off. The MSM6242B is offered in a 18-pin plastic DIP and a 24-pin plastic Small Outline package.
FEATURES
DIRECT MICROPROCESSOR/MICROCONTROLLER BUS CONNECTION TIME 23:59:59 MONTH 12 DATE 31 YEAR 80 * * * * * * DAY OF WEEK 7
* 4-bit data bus * 4-bit address bus * READ, WRITE, ALE and CHIP SELECT INPUTS * Status registers - IRQ and BUSY * Selectable interrupt outputs - 1/64 second, 1 second, 1 minute, 1 hour * Interrupt masking * 32.768 KHz crystal controlled operation
12/24 hour format Auto leap year 30 second error correction Single 5V supply Battery backup down to VDD = 2.0V Low power dissipation: 20W max at VDD = 2V 150W max at VDD = 5V * 18 pin Plastic DIP (DIP18-P-300) * 24 Pin-V Plastic SOP (SOP24-P-430-VK)
23
MSM6242B FUNCTIONAL BLOCK DIAGRAM
Semiconductor
XT 32.768KHz XT OSC COUNTER 1 Hz
RESET STOP 30 ADJ HOLD BUSY bit bit bit bit bit 30 sec ADJ bit
GATE
D3 D2 D1 D0 WR RD A3 A2 A1 A0 CS0 ALE CS1
24/12bit MI1 MI10 H1 H10 W
S1 S10
GATE
D1 D10
MO1MO10
Y1 Y10 64Hz 1-sec carry 1-min carry 1-hour carry STDP
GATE & LATCH
DECODER
S1 S CF
CD
CE
CF
* S1~W~Y10 are time counter register * C0~CF are control register
PIN CONFIGURATION
STD.P CS0 ALE A0 A1 A2 A3 RD GND
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDD XT XT CS1 D0 D1 D2 D3 WR
STD.P CS0 NC ALE A0 NC A1 NC A2 A3 RD GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD XT XT NC CS1 D0 NC NC D1 D2 D3 WR
A0-A3: D0-D3: CSO , CS1: RD: WR: ALE: STD.P: XT, XT: VDD: VSS:
Address input Data input/output CHIP SELECTS 0,1 READ enable WRITE enable Address latch enable Standard pulse output XTAL oscillator input/output +5V supply ground
18 pin Plastic DIP
24 pin Plastic Small Outline Package
24
Semiconductor REGISTER TABLE
Address Input Register Address Input A3 A2 A1 A0 Name 0 1 2 3 4 5 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 S1 S10 MI1 MI10 H1 H10 D1 D10 MO1 MO10 Y1 Y10 W Data D3 S8 * mi8 * h8 D2 S4 S40 mi4 mi40 h4 PM/ AM d4 * mo4 * y4 y40 w4 D1 S2 S20 mi2 mi20 h2 h20 d2 d20 mo2 * y2 y20 w2 D0 S1 S10 mi1 mi10 h1 h10 d1 d10 mo1 MO10 y1 y10 w1 Count value 0 to 9 0 to 5 0 to 9 0 to 5 0 to 9 0 to 2 or 0 to 1 0 to 9 0 to 3 0 to 9 0 to 1 0 to 9 0 to 9 0 to 6
MSM6242B
Description 1-second digit register 10-second digit register 1-minute digit register 10-minute digit register 1-hour digit register PM/AM, 10-hour digit register 1-day digit register 10-day digit register 1-month digit register 10-month digit register 1-year digit register 10-year digit register Week register
*
6 7 8 9 A B C
0 0 1 1 1 1 1
1 1 0 0 0 0 1
1 1 0 0 1 1 0
0 1 0 1 0 1 0
d8 * mo8 * y8 y80 * 30 sec. ADJ
D
1
1
0
1
CD
IRQ FLAG
BUSY
HOLD
--
Control Register D
E F
1 1
1 1
1 1
0 1
CE CF
t1
t0
ITRPT MASK /STND STOP REST
-- --
Control Register E Control Register F
TEST
24/12
REST = RESET ITRPT/STND = INTERRUPT/STANDARD Note 1) Note 2) Note 3) Note 4) Bit * does not exist (unrecognized during a write and held at "0" during a read). Be sure to mask the AM/PM bit when processing 10's of hour's data. BUSY bit is read only. The IRQ FLAG bit can only be set to a "0". Setting the IRQ FLAG to a "1" is done by hardware. PM at 1 and AM at 0 for PM / AM bit. Figure 1. Register Table
25
MSM6242B OSCILLATOR FREQUENCY DEVIATIONS
Semiconductor
0
1 0
Ta = 25C
f/f (PPM)
f/f (PPM) 5V 2V 20 40 60 80
-1 -2 -3 -4
-50
-100 -60
-40
-20
0
0
1
2
3 VDD (V)
4
5
6
Ta (C)
Figure 2. Frequency Deviation (PPM) vs Temperature
Figure 3. Frequency Deviation (PPM) vs Voltage
Note:
1. The graghs above showing frequency deviation vs temperature/voltage are primarily characteristic of the MSM6242B with the oscillation circuit described below.
XT
XT Crystal: Type N0, P3 by kinseki (32.768 KHz) CG, CD: 22pF (Temperature Characteristics: 0)
CG
CD VDD
26
Semiconductor ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Storage Temperature Symbol VDD VI VO TSTG Ta = 25C Condition Rating -0. 3 to 7 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -55 to +150
MSM6242B
Unit V V V C
OPERATING CONDITIONS
Parameter Power Supply Voltage Standby Supply Voltage Crystal Frequency Operating Temperature Symbol VDD VBAK f(XT) TOP Condition -- -- -- -- Rating 4 to 6 V 2 to 6 32.768 -40 to +85 kHz C Unit
D.C. Characteristics
(VDD = 5V 10%, TA = -40 ~ +85) Parameter "H" Input Voltage "L" Input Voltage Symbol VIH1 VIL1 Condition -- -- Min. 2.2 -- Typ. -- -- Max. -- V 0.8 Unit Applicable Terminal All input terminals except CS1, XT Input terminals other than D0 ~ D3, XT D0 ~ D3 V 2.4 -- -- -- -- -- 4/5VDD -- -- -- -- 5 -- -- -- -- -- 0.4 10 -- 30 A 10 -- 1/5VDD VDD V A PF STD.P All input terminals D0 ~ D3
Input Leak Current
ILK1
VI = VDD/0V
--
--
1/-1 A
Input Leak Current "L" Output Voltage "H" Output Voltage "L" Output Voltage OFF Leak Current Input Capacitance Current Consumption Current Consumption "H" Input Voltage "L" Input Voltage
ILK2 VOL1 VOH VOL2 IOFFLK CI IDD1 IDD2 VIH2 VIL2 IOL = 2.5mA IOH = -400A IOL = 2.5mA V = VDD/0V Input frequency 1MHz f(xt) = 32.768 KHz ~ CS1 ~ 0 VDD = 5V VDD = 2V
-- --
-- --
10/-10 0.4
VDD = 2 ~ 5.5V
V
CS1
27
MSM6242B SWITCHING CHARACTERISTICS
(1) WRITE mode (ALE = VDD)
Semiconductor
(VDD = 5V 10% Ta = -40 to +85C) Parameter CS1 Set up Time CS1 Hold Time Address Stable Before WRITE Address Stable After WRITE WRITE Pulse Width Data Set up Time Data Hold Time RD / WR Recovery Time Symbol tC1S tC1H tAW tWA tWW tDS tDH tRCV Condition -- -- -- -- -- -- -- -- Min. 1000 1000 20 10 120 100 10 60 Max. -- -- -- -- -- -- -- -- Unit
ns
CS1 A0 ~ A3 CS0 WR D0 ~ D3 (INPUT)
VIH2 - VIH1 - VIL1 - VIH1 - VIH1 - VIL1 - tC1S
,, , ,, ,, ,, ,,
tC1H tWW
,, , ,, , tWA ,,
,
tAW
,, ,,
tDS
tDH
,,
tRCV , ,,
,,
,,
,,
,,
,, ,, ,, ,, ,, ,, ,,
,,
VIH1 = 2.2V VIL1 = 0.8V VIH2 = 4/5VDD VIL2 = 1/5VDD
,,
,
Figure 4. Write Cycle -- (ALE = VDD)
(2) WRITE mode (With use of ALE)
(VDD = 5V 10%, Ta = -40 ~ +85C) Parameter CS1 Set up Time Address Set up Time Address Hold Time ALE Pulse Width ALE Before WRITE WRITE Pulse Width ALE After WRITE DATA Set up Time DATA Hold Time CS1 Hold Time RD / WR Recovery Time Symbol tC1S tAS tAH tAW tALW tWW tWAL tDS tDH tC1H tRCV Condition -- -- -- -- -- -- -- -- -- -- -- Min. 1000 25 25 40 10 120 20 100 10 1000 60 Max. -- -- -- -- -- -- -- -- -- -- -- ns Unit
28
Semiconductor
MSM6242B
tC1S CS1 A0 ~ A3 CS0 ALE WR D0 ~ D3 (INPUT) VIH2 - VIH1 - VIL1 - VIH1 - VIL1 - VIH1 - VIL1 - VIH1 - VIL1 -
,, , ,, ,,
tAS
,, , ,,
,,
,,
tC1H VIH1 = 2.2V VIL1 = 0.8V VIH2 = 4/5VDD VIL2 = 1/5VDD
,,
tAH
,, ,
,,
,,
tAW
,, ,, ,, ,, ,, ,,
tALW
,,
tWW tDS
,,
,,
,
tWAL t ,, ,, RCV , tDH,,,,, ,, ,
,,
,
,,
,, ,, ,, ,
Figure 5. Write Cycle -- (With Use of ALE)
(3) READ mode (ALE = VDD)
(VDD = 5V 10%, Ta = -40 to +85C) Parameter CS1 Set up Time CS1 Hold Time Address Stable before READ Address Stable after READ RD to Data Data Hold RD / WR Recovery Time Symbol tC1S tC1H tAR tRA tRD tDR tRCV Condition -- -- -- -- CL = 150pF -- -- -- 0 60 Min. 1000 1000 20 0 Max. -- -- -- ns -- 120 -- -- Unit
CS1 A0 ~ A3 CS0 RD D0 ~ D3 (OUTPUT)
VIH2 - VIH1 - VIL1 - VIH1 - VIL1 - VOH - VOL - tC1S
,, , ,, ,, ,
tAR
,, ,, ,,
tRA
,, , ,,
tC1H
,, ,, ,
,, tRCV,,,
tRD
,, ,, , ,, ,, ,, ,, ,,
tDR
,, ,, ,
"Z"
,, ,
VIH1 = 2.2V VIL1 = 0.8V VIH2 = 4/5VDD VIL2 = 1/5VDD VOH = 2.2V VOL = 0.8V
Figure 6. Read Cycle -- (ALE = VDD)
29
MSM6242B
(4) READ mode (With use of ALE)
Semiconductor
(VDD = 5V 10%, Ta = -40 to +85C) Parameter CS1 Set up Time Address Set up Time Address Hold Time ALE Pulse Width ALE before READ ALE after READ RD to Data DATA Hold CS1 Hold Time RD / WR Recovery Time Symbol tC1S tAS tAH tAW tALR tRAL tRD tDR tC1H tRCV Condition -- -- -- -- -- -- CL = 150pF -- -- -- Min. 1000 25 25 40 10 10 -- 0 1000 60 Max. -- -- -- -- -- -- 120 -- -- -- ns Unit
CS1 A0 ~ A3 CS0 ALE RD D0 ~ D3 (OUTPUT)
VIH2 - VIH1 - VIL1 - VIH1 - , VIL1 ,- VIH1 - VIL1 - VOH - VOL - tC1S
,, ,,
tAS
,, ,, ,, ,
tAH
,, ,,
tC1H VIH1 = 2.2V VIL1 = 0.8V VIH2 = 4/5VDD VIL2 = 1/5VDD VOH = 2.2V VOL = 0.8V
,, ,
tAW
,, ,, ,, , ,, ,
tALR
,, , ,, ,, ,,
tRAL tRCV ,, ,, tDR,,,,,, ,, ,
tRD
, ,, ,, ,, ,, ,,
"Z"
Figure 7. Read Cycle -- (With Use of ALE)
30
Semiconductor
MSM6242B
PIN DESCRIPTION
Name D0 D1 D2 D3 A0 A1 A2 A3 ALE Pin No. RS GS 14 13 12 11 4 5 6 7 3 19 16 15 14 5 7 9 10 4 Address input pin for use by a microcomputer to select internal clock/calendar's registers and control registers for Read/Write operations (See Function Table Figure 1). Address input pins A0-A3 are used in combination with ALE for addressing registers. Address Latch Enable pin. This pin enables writing of address data when ALE = 1 and CSO = 0; address data is latched when ALE = 0 Microcontroller/Microprocessors having an ALE output should connect to this pin; otherwise it should be connected at VDD Writing of data is performed by this pin. When CS1 = 1 and CSO = 0, D0 ~ D3 data is written into the register at the rising edge of WR. Reading of register data is accomplished using this pin. When CS1 = 1, CSO = 0 and RD = 0, the data of this register is output to D0 ~ D3. If both RD and WR are set at 0 simaltaneously, RD is to be inhibited. Chip Select pins. These pins enable/disable ALE, RD and WR operation. CSO and ALE work in combination with one another, while CS1 work independent with ALE. CS1 must be connected to power failure detection as shown in Figure 18. Output pin of N-CH OPEN DRAIN type. The output data is controlled by the D1 data content of CE register. This pin has a priority to CSO and CS1. Refer to Figure 9 and FUNCTIONAL DESCRIPTION OF REGISTERS. 32.768 kHz crystal is to be connected to these pins. When an external clock of 32.768 kHz is to be used for MSM6242's oscillation source, either CMOS output or pull-up TTL output is to be input from XT, while XT should be left open. Power supply pin. +2 ~ +6V power is to be applied to this pin. Ground pin.
RFB 5M XT X'tal C1 VDD OR GND C2 XT C1 = C2 = 15 ~ 30pF 32.768 kHz N-CH STD.P OUTPUT VDD
Description Data Input/Output pins to be directly connected to a microcontroller bus for reading and writing of the clock/calendar's registers and control registers. D0 = LSB and D3 = MSB.
WR
10
13
RD CS0 CS1
8 2 15
11 2 20
STD.P
1
1
XT XT VDD GND
16 17 18 9
22 23 24 12
The impedance of the crystal should be less than 30k
Figure 8. Oscillator Circuit
Figure 9.
31
MSM6242B FUNCTIONAL DESCRIPTION OF REGISTERS
S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1, Y10, W a) b) c) d)
Semiconductor
e)
f)
These are abbreviations for SECOND1, SECOND10, MINUTE1, MINUTE10, HOUR1, HOUR10, DAY1, DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These values are in BCD notation. All registers are logically positive. For example, (S8, S4, S2, S1) = 1001 which means 9 seconds. If data is written which is out of the clock register data limits, it can result in erroneous clock data being read back. PM/AM, h20, h10 In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the setting of 12-hour mode h20 is to be set. Otherwise it causes a discrepancy. In reading out the PM/AM bit in the 24-hour mode, it is continuously read out as 0. In reading out h20 bit in the 12-hour mode, 0 is written into this bit first, then it is continuously read out as 0 unless 1 is being written into this bit. Registers Y1, Y10, and Leap Year. The MSM6242B is designed exclusively for the Christian Era and is capable of identifying a leap year automatically. The result of the setting of a nonexistant day of the month is shown in the following example: If the date February 29 or November 31, 1985, was written, it would be changed automatically to March 1, or December 1, 1985 at the exact time at which a carry pulse occurs for the day's digit. The Register W data limits are 0 - 6 (Tabel 1 shows a possible data definition).
TABLE 1 w4 0 0 0 0 1 1 1
Using HOLD Bit
w2 0 0 1 1 0 0 1
w1 0 1 0 1 0 1 0
Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday
Not Using HOLD Bit
HOLD Bit 1
Read Register S1 ~ W Data of DATA S1 ~ W Register NO HOLD Bit 0 * In the inside of LSI, the CLEAR of BUSY bit is performed when HOLD bit = 0, but, if the period of HOLD bit =0 is extermely narrow as compared with the period of HOLD bit = 1, there is some case that the CLEAR of BUSY bit delays so that the BUSY bit can be cleared by sampling HOLD bit = 0 at approximate 16KHz. It is recommended to allow an idling time of 62ms or more. * Read Register S1 ~ W DATA1 = DATA2
First
Read BUSY Bit
Busy Bit= O? YES Write data into or Read data from registers S1 ~ W
Second
Idling Time
DATA1 = DATA2 YES
NO
HOLD Bit 0
Figure 10. Reading and Writing of Registers S1 ~ W
32
Semiconductor
MSM6242B
Reading Method 2 when Not Using HOLD Bit Initialization only at power ON * *1 and *2 represent the minimum required time out. For example t1 = 0 and tO = 1 when required to a unit of second; t1 = 1 and tO = 0 when required to a unit of minute; and t1 = 1 and tO = 1 when required to a unit of hour;
Reading Method 3 when Not Using HOLD Bit Initialization only at power ON * *1 and *2 represent the minimum required time unit. *1 t1 For example t0 *2 t1 = 0 and tO = 1 when required to a ITRPT/STNT 1 unit of second; 0 MASK t1 = 1 and tO = 0 when required to a CPU senses the unit of minute; and interruption. t1 = 1 and tO = 1 when required to a unit of hour; REGISTER CD READ
*1 t1 t0 *2 ITRPT/STNT MASK
1 0
IRQ FLAG
0
WAIT t See Note below TIME DATA READ Retried the reading, since a carry occurred during the operation. IRQ FLAG = 1 YES WAIT t NO The other IC causes the interruption. The interruption is caused by this IC due to the occurrence of a carry.
REGISTER CD READ NO (Note) YES Normal read t1 = 0 and tO = 1 . . . Less than 1 second t1 = 1 and tO = 0 . . . Less than 1 minute t1 = 1 and tO = 1 . . . Less than 1 hour t : 12 HOUR MODE . . . 35S 24 HOUR MODE . . . 3S Do this process within the following time requirements by combination between t1 and t0:
TIME DATA READ The IRQ FLAG is cleared to read the next time data.
IRQ FLAG = 0
IRQ FLAG
0
END
CD REGISTER (Control D Register) a) Setting this bit to a "1" inhibits the 1Hz clock to the S1 counter, at which time the Busy status bit can be read. When Busy = 0, register's S1 ~ W can be read or written. During this procedure if a carry occurs the S1 counter will be incremented by 1 second after HOLD = 0 (this condition is guaranteed as long as HOLD = 1 does not exceed 1 second in duration). If CS1 = 0 then HOLD = 0 irrespective of any condition. BUSY (D1) - Status bit which shows the interface condition with microcontroller/ microprocessors. As for the method of writing into and reading from S1 ~ W (address ~ C), refer to the flow chart described in Figure 10. IRQ FLAG (D2) - This status bit corresponds to the output level of the STD.P output. When STD.P = 0, then IRQ = 1; when STD.P = 1, then IRQ = 0. The IRQ FLAG indicates that an interrupt has occurred to the microcomputer if IRQ = 1. When D0 of register CE (MASK) = 0, then the STD.P output changes according to the timing set by D3 (t1) and D2 (t0) of register E. When D1 of register E (ITRPT/STND) = 1 (interrupt mode), the STD.P output remains low until the IRQ FLAG is written to a "0". When IRQ = 1 and timing for a new interrupt occurs, the new interrupt is ignored. When ITRPT/STND = 0 (Standard Pulse Output mode) the STD.P output remains low until either "0" is written to the IRQ FLAG; otherwise, the IRQ FLAG automatically goes to "0" after 7.8125ms. When writing the HOLD or 30 second adjust bits of register D, it is necessary to write the IRQ FLAG bit to a "1". 30 ADJ (D3) - When 30-second adjustment is necessary, a "1" is written to bit D3 during which time the internal clock registers should not be read from or written to 125s after bit D3 = 1 it will automatically return to a "0", and at that time reading or writing of registers can occur. 33 HOLD (D0) -
b) c)
d)
MSM6242B
Semiconductor
START
START
30-SECOND ADJ BIT = 1 READ 30-SECOND ADJ BIT
30-SECOND ADJ BIT = 1
125s PASS? YES END (B)
NO
30-SECOND ADJ BIT = 0? YES END (A)
NO
Figure 11. Writing 30-Second Adj. bit (Two Ways A, B)
CE REGISTER (Control E Register) a) MASK (D0) - This bit controls the STD.P output. When MASK = 1, then STD.P = 1 (open); when MASK = 0, then STD.P = output mode. The relationship between the MASK bit and STD.P output is shown Figure 12. The ITRPT/STND input is used to switch the STD.P output between its two modes of operation, interrupt and Standard timing waveforms. When ITRPT/STND = 0 a fixed cycle waveform with a low-level pulse width of 7.8125ms is present at the STD.P output. At this time the MASK bit must equal 0, while the period in either mode is determined by T0 (D2) and T1 (D3) of Register E. These two bits determine the period of the STD.P output in both interrupt and Fixed timing waveform modes. The tables below show the timing associated with the T0, T1 inputs as well as their relationship to INTRPT/STND and STD.P.
"1" "0" "INTERRUPT" DOES NOT OCCUR BECAUSE MASK BIT IS "1" OPEN LOW LEVEL "INTERRUPT" TIMING WRITE "0" INTO IRQ FLAG BIT INTRT/STND BIT = "1" INTRT/STND BIT = "0" "1" MASK BIT STD.P OUTPUT "0" "0" "1" OUTPUT DOES NOT OCCUR AT LOW LEVEL BECAUSE MASK BIT IS "1" OPEN LOW LEVEL OUTPUT TIMING AUTOMATIC RETURN
b)
ITRPT/STND (D1) -
c)
T0 (D2), T1 (D3) -
"1" MASK BIT "0"
STD.P OUTPUT
Figure 12. TABLE 2 t1 0 0 1 1 t0 0 1 0 1 Period 1/64 second 1 second 1 minute 1 hour Duty CYCLE of "0" level when ITRPT/STND bit is "0". 1/2 1/128 1/7680 1/460800
34
Semiconductor
MSM6242B
The timing of the STD.P output designated by T1 and T0 occurs the moment that a carry occurs to a clock digit.
(EXAMPLE) WHEN t1 = 1, t0 = 1 and MASK = 0. PM12:00 PM1:00 OPEN LOW LEVEL OPEN LOW LEVEL
WHEN ITRPT/STND BIT is "1" STD.P OUTPUT WHEN ITRPT/STND BIT is "0"
d) e) f) g) h)
The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125ms independent of T0/T1 inputs. The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time base. (See Figure 14). During 30 second adjustment a carry can occur that will cause the STD.P output to go low when T0/T1 = 1,0 or 1,1. However, when T1/T0 = 0, 0 and ITRPT/STND = 0, carry does not occur and the STD.P output resumes normal operation. The STD.P output is held (frozen) at the point at which STOP = 1 while ITRPT/STND = 0. No STD.P output change occurs as a result of writing data to registers S1 ~ H1.
CF REGISTER (Control F Register) a) REST (D0) - "RESET" STOP (D1) - This bit is used to clear the clock's internal divider/counter of less than a second. When REST = 1, the counter is Reset for the duration of REST. In order to release this counter from Reset, a "0" must be written to the REST bit. If CSI = 0 then REST = 0 automatically. The STOP FLAG Only inhibits carries into the 8192Hz divider stage. There may be up to 122s delay before timing starts or stops after changing this flag; 1 = STOP/0 = RUN.
"1" STOP BIT "0" "0" "1" "0" "1" "0"
b)
TIMING OF "CARRY" TO 8192Hz "CARRY" EXECUTED "CARRY" NOT EXECUTED
Figure 13
c)
24/12 (D2) - "24/HOUR/ 12 HOUR"
d)
TEST (D3) -
This bit is for selection of 24/12 hour time modes. If D2 = 1-24 hour mode is selected and the PM/AM bit is invalid. If D2 = 0-12 hour mode is selected and the PM/AM bit is valid. Setting of the 24/12 hour bit is as follows: 1) REST bit = 1 2) 24/12 hour bit = 0 or 1 3) REST bit = 0 * REST bit must = 1 to write to the 24/12 hour bit. When the TEST flag is a "1", the input to the SECONDS counter comes from the counter/divider stage instead of the 15th divider stage. This makes the SECONDS counter count at 5.4163KHz instead of 1Hz. When TEST = 1 (Test Mode) the STOP & REST (Reset) flags do not inhibit internal counting. When Hold = 1 during Test (Test = 1) internal counting is inhibited; however, when the HOLD FLAG goes inactive (Hold = 0) counter updating is not guaranteed. 35
MSM6242B
Semiconductor
TYPICAL APPLICATION INTERFACE WITH MSM6242B AND MICROCONTROLLERS
8085 AD3 AD2 AD1 AD0
MSM6242B D3 D2 D1 D0 A3 A2 A1 A0 CS0
R1 R2
8085 A/D A8 ~ A12
MSM6242B D3 D2 D1 D0 A3 A2 A1 A0 CS0
R1 R2
A8 ~ A15 S1 S0 IO/M ALE RD WR
A8 ~ A15 S1 S0 IO/M RD WR
DECODER
DECODER
ALE RD WR
ALE RD WR
MEMORY MAPPED
MSM6242B, R1 and R2 are not required.
I/O MAPPED
Note : If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of
Figure 15. Z80 D3 D2 D1 D0 A3 A2 A1 A0 A4 ~ A15 IORQ MREQ RD WR MSM6242B D3 D2 D1 D0 A3 A2 A1 A0 VDD G1 G2 CS0 ALE RD WR BUS 4-7 ALE RD WR MCS48 BUS3 BUS2 BUS1 BUS0 MSM6242B D3 D2 D1 D0 A3 A2 A1 A0 CS0 ALE RD WR
DECODER
DECODER
Note : It depends upon the switching characterisrics decided by a X'tal used for a Z80 that either of IORQ and MREQ is used.
Figure 16.
Figure 17.
36
Semiconductor TYPICAL APPLICATIONS -- INTERFACE WITH MSM80C49
MSM6242B
100f 3.9V 5 LITHIUM BATTERY 5 4.7f (tantalum)
22pf
2
X1
26 VDD INT
ALE RD
6 11 8 10
4.553 KHz 3 X2
22pf
WR MSM 80C49RS DB0 40 VCC DB1 DB2 DB3 1 T0 DB7 38 P27
12 13 14 15 19 34 820
P17 VSS 20
5 (VFWD = < 0.3V) i.e. GERMANIUM DIODE 18 18K 15pf VDD 17 1 XT SDT.P 3 ALE 32.768 KHz 8 RD 16 10 XT WR 5-35pf MSM 6242BRS 4/14 A/D0 5/13 A/D1 6/12 A/D2 7/11 A/D3 2 CS0 15 CS1 9 TR1 VSS 10K
1.8K 1.8K 220 1.8K 5 10f 220 5.2V 1.8K TR2
5
1.8K TR3
TR1 = 2N2907 TR2 = 2N2907 TR3 = 2N2222 5 = 1N4148
RS232 DB25 CONNECTOR
2 3 7 5 20
RS232 INTERFACE
Figure 18.
37
MSM6242B APPLICATION NOTE
1. Power Supply
START VDD = 5V
Semiconductor
Power On
STD.P Output = undifined
TEST Bit 0 REST Bit 0 24/12 Bit 1* STOP Bit 1 REST Bit 0 24/12 Bit 2* Set the current time HOLD Bit 0 STOP Bit 0
1* = 2* (1 or 0)
Start Operation
2. Adjustment of Frequency
VDD Screwdriver 18 17 16
VDD
VDD XT XT CD, CF = (0, 0, 0, 0) CE = (t1, t0, 0, 0) SDT.P 1 2 3
d
c
Frequency counter
b Eye
2 1
0.1 INCH
CD ~ CF are to be set at as described in the figure and the capacitor is to be adjusted to meet the settle frequency of t0 and t1. If the right oscillation can not be obtained, 1. Check the waveform of XT 2. Check CD ~ CF content 3. Check the noise
VDD
XT
XT
1
a a b
2
0.3 INCH 0.2 INCH
: INHIBIT
38
Semiconductor
3. CH1 (Chip Select)
MSM6242B
VIH and VIL of CH1 has 3 functions. a) To accomplish the interface with a microcontroller/microprocessor. b) To inhibit the control bus, data bus and address bus and to reduce input gate pass current in the stand-by mode. c) To protect internal data when the mode is moved to and from standby mode. To realize the above functions: a) More than 4/5 VDD shoud be applied to the MSM6242B for the interface with a microcontroller/microprocessor in 5V operation. b) In moving to the standby mode, 1/5 VDD should be applied so that all data buses should be disabled. In the standby mode, approx. 0V should be applied. c) To and from the standby mode, obey following Timing chart.
To Standby Mode 4 ~ 6V VDD 4V 2 ~ 4V 2s (MIN) CS1 2V 5 DD 1 V 5 DD 4 V 5 DD 4V 2s (MIN) From Standby Mode
CS0 : H or WR : H
4. Set SDT.P at alarm mode
Set alarm at 9:00 MASK BIT 0 ITRPT/STND BIT 1 t1, t0 1 Read Register CD
Start interruption CPU Activation
D2 = 1? YES Read H10 and H10 Cotent
NO
Repeat
AM 9:00? YES
NO
CPU HALT or CPU STAND BY
39
MSM6242B TYPICAL APPLICATION -- POWER SUPPLY CIRCUIT
Semiconductor
VCE (SAT.) = 0.1V +5V
RIPPLE OPERATING: 20mV P-P BATTERY BACKUP: 0mV 22f 4.7f VDD
+5V
RL
RL M
C
100 4.7f VDD MSM 6242B VSS
51K
10K
100 1.2 x 3 = 3.6V Ni - Cd
MSM 6242B VSS
B 1.5 x 2 = 3V DRY CELLS
10K Figure 20.
Figure 19.
220
~ 6.5V
VDD MSM 6242B VSS 4.7f
100 RL 1.2 x 3 = 3.6V Ni - Cd
D1 +5V
Figure 21.
4.7F: tantalum
SUPPLEMENTARY DESCRIPTION * When "0" is written to the IRQ FLAG bit, the IRQ FLAG bit is cleared. However, if "0" is assigned to the IRQ FLAG bit when written to the other bits, the 30-sec ADJ bit and the HOLD bit, the IRQ FLAG = 1 and was generated before the writing and IRQ FLG = 1 generated in a moment then will be cleared. To avoid this, always set "1" to the IRQ FLAG unless "0" is written to it intentionally. By writing "1" to it, the IRQ FLAG bit does not become "1". Since the IRQ FLAG bit becomes "1" in some cases when rewriting either of the t1, t0, or ITRPT/STND bit of register CE, be sure to write "0" to the IRQ FLAG bit after writing to make valid the IRQ FLAG = 1 to be generated after it. The relationship between SDT.P OUT and IRQ FLAG bit is shown below:
open STD.P OUT IRQ FLAG bit "L" 1 0 approx. 1.95 ms
*
*
40

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